The complexity of integrated circuits (ICs) being designed nowadays is continuously increasing and has resulted in complete system-on-chip (SoC) solutions. Even more, the complexity of such integrated systems is exploding thanks to advances in process fabrication. The limiting factor is now the ability to design, manage and verify such systems rather than the ability to fabricate them.
As SoC's are becoming larger, the only way to efficiently design such dense SoC's, both from the design complexity and time-to-market aspects, is by embedding Intellectual Property (IP) cores. Standards for such cores are currently evolving. Ideally, they should be reusable, pre-characterized and pre-verified. But as fabrication technology changes, it is desirable to convert or migrate the design to the new process parameters. For example, an IP core may be designed and tested for 90 nm technology, but it is desirable to convert the IP core to a new process of 60 nm technology.
IP reuse methodologies are readily available for digital blocks, thanks to the well-structured and cell-based design characteristics of the digital world. This is completely different on the analog side, where each circuit block (which may contain thousands of devices) is carefully redesigned from scratch each time. The main obstacle for analog IP migration is that analog design is highly sensitive to device physical parameters and parasitics and to global technology constraints. This makes the retargeting of an analog portion of any design a tough task and is still a manual process.
Several approaches for analog reuse has been implemented in previous work and most of them rely on optimization techniques. The optimization engine visits candidate circuit designs and adjusts their parameters in an attempt to satisfy their user's specified performance goals. A first group of optimization techniques use analytical models that describe the basic performance of the circuit using symbolic equations. A second group of optimization techniques uses the full spice accuracy. Using a full analog simulator capability has the advantage of accurate results but suffers from being very slow, since it has to perform lengthy transient simulation over and over to evaluate the performance of the circuit and make sure it satisfies the target goals. On the other hand, using analytical equations has the impact of less accurate designs with faster results. Nonetheless, neither of these techniques is ideal as there is a need for increased accuracy and speed.
Another problem with the prior-art techniques is that they are closer to a circuit re-design than design reuse. All design knowledge and tradeoffs, implicitly coded by the first designer in the initial design are completely lost. In addition, optimization-based techniques are only adapted to cell sizing due to extensive use of computer resources. Therefore, the prior-art techniques are less suitable for migrating a complete mixed-signal function (e.g., analog-to-digital converter, PLL, . . . )
Thus, it is desirable to provide an analog design retargeting system that has the ability to take an already designed, sized and verified circuit in a source technology and map it to a different target technology while preserving the same general architecture and performance characteristics.